1. Technical Field
The present invention relates to a high voltage output circuit of a semiconductor device. More particularly, the present invention is directed to a pull-up transistor array for a high voltage output circuit.
2. Description
A semiconductor device has an output circuit for receiving a signal from external parts or other circuits in the device to output a signal of a predetermined level. The output circuit includes a level shift circuit and pull-down and pull-up transistors. In the level shift circuit, the signal inputted to the output circuit is shifted to a predetermined voltage level. The pull-up and pull-down transistors receive an outputted signal from the level shift circuit to output a low level voltage VSS or a high level voltage VDD, respectively.
FIG. 1 is a view of a conventional output circuit with PMOS pull-up and NMOS pull-down transistors.
Referring to FIG. 1, a semiconductor device has an output circuit for receiving signals to output a voltage having a predetermined level. Each signal inputted to an input port IN n is inputted to a level shift circuit L/S n. Next, the signal is shifted to a voltage having a predetermined level to be inputted to the gate electrodes of pull-up and pull-down transistors 2 and 4. The high level voltage VDD is supplied to the source of the PMOS pull-up transistor 2 and the low level voltage VSS is supplied to the source of the NMOS pull-down transistor 4. The drain of the pull-up transistor 2 and the drain of the pull-down transistor 4 are connected to an output port OUP n to output the predetermined voltage level.
If a pull-up signal is outputted from the level shift L/S n, the pull-down transistor 4 is turned off and the pull-up transistor 2 is turned on. Thus, the output circuit outputs the high level voltage VDD. On the other hand, if a pull-down signal is outputted from the level shift L/S n, the pull-up transistor 2 is turned off and the pull-down transistor 4 is turned on. Thus, the output circuit outputs the low level voltage VSS.
FIG. 2 is a view of a conventional output circuit having the NMOS pull-up and NMOS pull-down transistors.
The output circuit of FIG. 2 has an NMOS pull-up transistor. Unlike the output circuit of FIG. 1 having the PMOS pull-up transistor, the output circuit of FIG. 2 having the NMOS pull-up transistor requires an additional circuit for inputting the pull-up and pull-down signals to the pull-up and pull-down transistors, respectively. However, in the case of the output circuit having the NMOS pull-up transistor, the area of the transistor is small and layout is easily achieved as compared with the output circuit having the PMOS pull-up transistor.
Referring to FIG. 2, each signal inputted into the input port IN n is inputted to the level shift circuit L/S n to be shifted to the predetermined voltage level. Next, like the output circuit having the PMOS pull-up transistor, the shifted signal is inputted to the gate electrode of the NMOS pull-up and NMOS pull-down transistors 6 and 8.
The high level voltage VDD is supplied to the drain of the NMOS pull-up transistor 6 and the low level voltage VSS is supplied to the source of the NMOS pull-down transistor 8. The source of the pull-up transistor 6 and the drain of the pull-down transistor 8 are connected to the output port OUT n to output the predetermined voltage level.
If the pull-up signal is outputted from the level shift L/S n, the pull-down transistor 8 is turned off and the pull-up transistor 6 is turned on. Thus, the output circuit outputs the high level voltage VDD. On the other hand, if the pull-down signal is outputted from the level shift L/S n, the pull-up transistor 6 is turned off and the pull-down transistor 8 is turned on. Thus, the output circuit outputs the low level voltage VSS.
FIG. 3 is a top plan view of the pull-up and pull-down transistor arrays for the output circuit having a conventional PMOS pull-up transistor.
Referring to FIG. 3, an N-well region 12 and a P-well region 10 are widely defined at the semiconductor substrate. PMOS transistors 16 are disposed at the N-well region 12 and NMOS transistors 14 are disposed at the P-well region 10. Typically, transistors having a same channel are disposed adjacent to one another in order to form easily a conductive well.
Although not shown in the figure, the source and drain of the transistors and the gate electrode are connected to an interconnection to constitute the output circuit. A gate electrode 18 of the NMOS transistor 14 and a gate electrode 20 of the PMOS transistor are connected to the level shift circuit. The high level voltage is supplied to a source 26 of the PMOS transistor 16 through the interconnection. The low level voltage is supplied to a source 22 of the NMOS transistor 14 through the interconnection. Also, a drain 28 of the PMOS transistor 16 and a drain 24 of the NMOS transistor 14 are opposite to each other, and are coupled to each other as well as to the output port through the interconnection.
As illustrated in FIG. 3, because a typical semiconductor device operates at an external input voltage of 5V or less, the pull-up and pull-down transistors have a general MOS transistor structure at the output circuit of the semiconductor device. However, the pull-up and pull-down transistors having the general MOS transistor structure cannot be used in the semiconductor device requiring a high voltage operation circuit such as a power device. This is because the pull-up and pull-down transistors cannot resist high voltage and current. Thus, the semiconductor device requiring the high voltage operation circuit includes a double diffused transistor (DMOS transistor) that is operable at the high voltage.
Accordingly, it would be advantageous to provide a pull-up transistor array for a high voltage output circuit in a semiconductor device where a high voltage operation is needed.
It would also be advantageous is to reduce an area of a pull-up transistor array by removing a device isolation region for isolation between transistors.
According to one aspect, the present invention provides a pull-up transistor array having double diffused transistors. The transistor array includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate and N double diffused MOS transistors (DMOS transistors) laterally arranged on the epitaxial layer. One of source/drains of the double diffused transistors is formed at each of the transistors, and the N double diffused MOS transistors share another source/drain.
In accordance with another aspect of the present invention, the DMOS transistor may be a vertical double diffused MOS transistor (VDMOS transistor). The pull-up transistor array includes a substrate of a first conductivity type and an epitaxial layer of a second conductivity type formed on the substrate. A buried layer of the second conductivity type is interposed between the substrate and the epitaxial layer. A plurality of looped insulating patterns is regularly spaced and arranged on the epitaxial layer in one direction. A gate pattern is formed over the epitaxial layer surrounded by the looped insulating patterns. The gate pattern partially overlaps on an upper portion of the looped insulating pattern. Also, the gate pattern has a mesh-shaped structure in which a plurality of openings is arranged two-dimensionally. A plurality of source regions is formed in the epitaxial layer exposed through the openings of the gate pattern. A drain region is formed in the epitaxial layer between the looped insulating patterns. The drain region is aligned to outer walls of the looped insulating patterns to be formed vertically in the epitaxial layer.
In accordance with another aspect of the present invention, the DMOS transistor may be a lateral double diffused MOS transistor (LDMOS transistor). The pull-up transistor array having a P-channel LDMOS transistor includes a substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on the substrate, and a plurality of first conductivity type wells formed in the epitaxial layer. The first conductivity type wells are regularly spaced and arranged in one direction. A second conductivity type well is formed in the epitaxial layer surrounding the first conductivity type wells. The second conductivity type wells have a ladder-shaped structure aligned to sidewalls of the first conductivity type wells. Looped gate patterns are formed on the epitaxial layer. The looped gate patterns overlap on the upper portion of the sidewalls of the first conductive wells. A looped insulating pattern is interposed between the epitaxial layer and the gate patterns. A source region is aligned to outer sidewalls of the looped insulating patterns to be formed in the second conductivity type well. A plurality of drain regions is aligned to inner sidewalls of the looped insulating patterns to be formed in the first conductivity type wells, respectively.